1. Field of the Invention
The present invention relates to a semiconductor device, and more specifically to a semiconductor device having fine complementary metal-oxide-semiconductor (CMOS) transistors and fine bipolar transistors which are fabricated in the same substrate. This semiconductor device is called "Bi-CMOS device" in the specification.
2. Description of Related Art
Lately, to realize a high access speed, a high integration density and a low power consumption in integrated circuits, Bi-CMOS devices are actively studied and reduced into practice which are composed of bipolar transistors which can realize a high access speed and CMOS transistors which can realize a high integration density and can operate with a low power consumption.
In conventional Bi-CMOS devices, however, the operation speed and the integration density have been limited mainly by the following three factors, namely, a gate electrode length of NMOS transistors and PMOS transistors, an emitter width of bipolar transistors, and a base resistance of the bipolar transistors. The base resistance of the bipolar transistors is substantially in proportion to a distance between an emitter diffused region and a so-called grafted base region for contact to a base electrode.
In the conventional Bi-CMOS devices, it has been difficult to reduce the gate electrode length to a value not greater than 1.0-1.3 .mu.m because of compatibility with reliability of devices and yielding in manufacturing. For the same reason, it has been difficult to reduce the emitter width to a value not greater than 1.0-1.3 .mu.m. In addition, the distance between the emitter diffused region and the grafted base region could not have been decreased to a value not greater than 2 or 3 .mu.m, because of limitation in accuracy of alignment and in accuracy of etching.
In a prior manufacturing process for bipolar transistors, Japanese Patent Application Laid-open Nos. Sho 60-81862 and Sho 60-89969 have proposed to use a Super Self-aligned process Technology (SST) for forming a base portion and an emitter portion in a self-alignment manner. However, the method disclosed in these Japanese applications has been effective only in fabricating a fine bipolar transistor integrated circuit. A manufacturing process for Bi-CMOS devices has to be applied commonly to formation of bipolar devices and formation of MOS devices so that the steps of manufacturing process are as less as possible.